//Basically a SR-flipflop with an enable bit so that the flipflop cannot be changed without first being enabled.  Reset of course still changes the flipflop to 0.
module FF (clk, reset, enable, set, q);

	input clk;
	input reset;
	input enable;
	input set;
	
	output q;

	//flipflops store a value
	reg bit;

	//change the value on the clock edge TODO is this right?
	always @(posedge clk) begin
		if(reset)
			bit <= 0;
		else if (enable)
			bit <= set;
	end

	//q is always bit
	assign q = bit;
			
endmodule
